Semiconductor Dynamic Random Access Memory (DRAM) devices have been applied widely in the integrated circuits with the advance of semiconductor manufacture. Typically, a memory cell consists of a storage capacitor and an access transistor for each bit to be stored by the semiconductor DRAM. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called the bit line and the word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
With the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. Namely, the amount of the charge capable of being stored by the capacitor decreases. Besides, for very small memory cells, planar capacitors produced has lower reliability in operation. Accordingly, the important issue is how to promote the capacitance and reliability of capacitors with the decreasing scale of the devices and the increasing integration of the integrated circuits.
For resolving the above problems, the manufacture of capacitors tends to increase the surface area of the storage electrode, and results in the development of the various types of capacitors such as the trench capacitor and the stacked capacitor. Besides, the high dielectric films are used for the capacitor. The MIM (metal/insulator/metal) structure capacitors are also used to substitute for the MIS (metal/insulator/silicon) structure capacitors gradually due to the MIM structure capacitors having the excellent conduction character and capacitance. Please refer to FIG. 1, a typical MIM structure capacitor is illustrated. An insulator layer 3 is formed on a semiconductor substrate 1, and a metal plug 7 is formed into the contact hole on the insulator layer 3 to connect electrically the bottom electrode 9 and the active devices (not shown) on the semiconductor substrate 1. A thin dielectric layer 11 is deposited along the surfaces of the bottom electrode 9 and the insulator layer 3. The top electrode 13 is formed on the thin dielectric layer 11. It is noted that a barrier layer 5 is formed along the contact hole firstly (namely along the sidewalls of the insulator layer 3 and the top surface of the substrate 1) before forming the metal plug 7 into the contact hole, to serve as an interface for promoting the junction efficiency between the metal plug 7 and the active devices.
In general, aluminum (Al) is used widely for forming the metal line since aluminum has the lower resistance and good adhension to dielectric materials. However, aluminum can not be fill into the contact holes effectively since the aluminum is always deposited by using the physical vapor deposition (PVD) method semiconductor in manufacture. Especially, it is more difficult to form the aluminum plug into the contact holes with higher aspect ratio.
Therefore, tungsten (W) plug is usually used to take the place of aluminum plug in the MIM structure capacitors in current semiconductor manufacture. Particularly, the tungsten can be deposited by using the chemically vapor deposition (CVD) method results in the step coverage ability of tungsten is better than that of aluminum. However, it is still difficult to form the tungsten plug effectively into the contact holes with the aspect retio more than 10:1. Besides, as described above, the requirement to form Ti/TiN film for serving as the barrier films cause the increasing difficulty to form tungsten plug into the contact holes.